1. Field of the Invention
The present invention generally relates to the manufacture of field effect transistor (FET) devices and, more particularly, to an improved isolation design which mitigates leakage current induced along the edges of an FET device, especially submicron FET devices using shallow trench isolation, and a unique phase shift mask used for making the FET device.
2. Description of the Prior Art
Metal oxide semiconductor field effect transistor (MOSFET) devices using deep or shallow trench isolation exhibit high off-current leakage, due to field enhanced lowering of threshold voltage, V.sub.t, at the isolation corners.
Simulated threshold roll-off of devices using two different isolation structures is shown in FIG. 1. The simulated data shown in FIG. 1 was generated assuming that everything else remains the same, such as the same implant condition, oxide thickness, work function, etc. The device using recessed oxide isolation (top curve) has the highest threshold voltage, V.sub.t. Its long channel (channel length.gtoreq.0.4.mu.) V.sub.t is in the range of 0.6-0.8 V. The lower curve is for a device with planar shallow trench isolation. Its long channel V.sub.t is in the range of 0.4-0.6 V.
One method of achieving acceptable off-current is by increasing the V.sub.t by tailored implant to the channel of the FET, particularly along the channel edges that abut the isolation region. However, such an approach results in increased V.sub.t away from the corners as well as at the corners, with a resultant loss of current drive.